Please use this identifier to cite or link to this item:
192.168.6.56/handle/123456789/77320Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Fook Lee, Weng | - |
| dc.date.accessioned | 2019-07-30T09:55:35Z | - |
| dc.date.available | 2019-07-30T09:55:35Z | - |
| dc.date.issued | 2003 | - |
| dc.identifier.uri | http://10.6.20.12:80/handle/123456789/77320 | - |
| dc.language.iso | en | en_US |
| dc.publisher | John Wiley & Sons, Inc | en_US |
| dc.subject | Verilog Coding for Logic Synthesis | en_US |
| dc.title | Verilog Coding for Logic Synthesis | en_US |
| dc.type | Book | en_US |
| Appears in Collections: | Mathematics | |
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